1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of testing the same. In particular, the present invention relates to a semiconductor integrated circuit including a racing circuit, and a method of testing the same.
2. Description of Related Art
In recent years, significant performance improvements in semiconductor integrated circuits have been achieved. Along with the performance improvements, it becomes more important than ever to secure the reliability of semiconductor integrated circuits.
Some of the semiconductor integrated circuits have a racing circuit incorporated therein. The incorporation of the racing circuit can provide a desired logical operation with a smaller number of clocks. When a delay fault is caused in the operation of the racing circuit, however, the semiconductor integrated circuit may not function normally.
Japanese Unexamined Patent Application Publication No. 10-242392 (hereinafter, referred to as “Patent Document 1”) discloses a technology for preventing racing from occurring between data and a clock signal.
As described above, when a delay fault is caused in the operation of a racing circuit, the semiconductor integrated circuit may not function normally. In view of this, in order to enhance the reliability of the semiconductor integrated circuit having the racing circuit incorporated therein, it is preferable to secure a sufficient time difference between timings at which the outputs of paths in a race condition are connected to a subsequent-stage circuit.
However, it is still not achieved to check, in a normal operation test for a semiconductor integrated circuit, whether there is a sufficient time difference between the timings at which the outputs of the racing paths are connected to the subsequent-stage circuit.